(1) Field of the Invention
The present invention relates to a circuit for compensating a linearity of an input/output characteristic of a parallel comparison type analog-to-digital converter (hereinafter simply referred to as an A/D converter).
(2) Background of the Art
In the above-described A/D converter, the input/output characteristic is often damaged due to a current flow through each comparator from a resistor chain for generating and outputting each comparison voltage to be compared with an input analog voltage.
Before explaining the linearity of the input/output characteristic in the A/D converter, a construction of the A/D converter will briefly be described.
An N-bit A/D converter generally includes parallel-connected comparators (a comparator group) having a number of 2.sup.N -1, series-connected resistors (a chain of resistors) having a number of 2.sup.N and equal resistance values for dividing a reference voltage (for example, -2 V) into comparison reference voltages having a number of 2.sup.N -1 and whose voltage values are mutually and sequentially different. Each comparison voltage is supplied to the corresponding comparator and each comparator compares the corresponding comparison voltage with an input analog voltage V.sub.IN for determining one of the comparison voltages which is nearest to the input voltage V.sub.IN. The converter includes an encoder for encoding the comparison result to derive an N-bit digital signal as the output of the A/D converter.
In addition, a linearity compensation circuit is provided for compensating the linearity of the input/output characteristic of the A/D converter affected due to a presence of a current flow to each comparator from the resistor chain for generating and outputting the comparison reference voltages. The resistor chain comprises the series-connected resistors.
In details, since all reference voltage dividing resistors in the resistor chain have mutually the same resistance values, terminal voltages across the respective resistors are mutually equal and a potential at a connection point between each resistor and its adjacent resistor becomes reduced by the same voltage value as the voltage is changed from the reference voltage supply side to a zero voltage side. Therefore, a characteristic curve representing a relationship between each resistor connecting point and a comparison voltage generated therefrom should have a perfect linearity.
However, since a constant current actually flows from the resistor chain to each comparator due to an input characteristic of each comparator, the current flowing through each resistor does not become even and the linearity of the comparison voltages will, therefore, be affected. This causes a worsened linearity of the above-described relationship input/output characteristic of the A/D converter and provides a source of errors in the output digital indication.
Consequently, it becomes necessary to compensate for the linearity by additionally supplying an auxiliary current to the conncecting point corresponding to an amount of the current which has flowed into the comparator group. The linearity compensating circuit serves as such a compensation as described above.
As the number of output terminals of the linearity compensation circuit connected to the resistor chain becomes increased, the compensation described above becomes more perfect.
If the number of output terminals from the compensation circuit is 255 which is one less than the number of resistors in the resistor chain of an 8-bit A/D converter for generating 256 comparison reference voltages and the amount of current by which each connecting point flows into the corresponding comparator is replenished so as to compensate for the current flowing through each corresponding comparator, a most perfect linearity will be achieved.
However, in this case, the construction of the whole linearity compensation circuit becomes complex and the construction of the A/D converter becomes accordingly large-sized. In addition, the power consumption of the whole A/D converter is increased.
One of improved linearity compensation circuits applied to the A/D converter has already been announced in a general national convention of Electronic and Communication Society of 1983 fiscal year (preliminary manuscripts, page 467) in Japan.
In the announced linearity compensation circuit, a section which determines a current of an ECL (Emitter-Coupled Logic) circuit used for the comparator group and encoder of the A/D converter is provided. In this section, a current flows into a main transistor thereof which is 384 times as great as the current denoted by i flowing into an input circuit of one comparator in the comparator group as an input current (base current). The magnitude of this current 384i is divided by six to derive six current flows 64i, 64i, 64i, 64i, 64i, and 64i by means of a current Miller circuit including four transistors. Then, three of the six currents (64i,64i, and 64i of the six-divided currents) are additionally supplied to three predetermined connecting points separated from one another by the number of the resistors of 64 in the resistor chain. It is noted that the currents which are 64 times as great as the above-described input current of each comparator are obtained by six and only three of these six currents are used for the linearity compensation. The remaining three currents are caused to flow wastefully through a minus terminal of the power supply of the linearity compensation circuit.
In this way, the previously announced linearity compensation circuit produces a current path through which a main current having a magnitude corresponding to a total current flow through all comparators in the A/D converter or corresponding to several times of the total current. In the above-described case, 384 represents 11/2 times of the total current (256i)) flows. The main current is divided into a plurality of subcurrents by means of the current Miller circuit. Some of the subcurrents are supplied to appropriate connecting points respectively in the resistor chain of the A/D converter to compensate for the input currents flowing into the comparators.
However, the previously announced linearity compensation circuit has a drawback of increased current loss and consequent increased power consumption.
This is because the above-described main current (384i) flowing through the above-described main transistor of the above-described section is divided into six subcurrents by means of the other three transistors constituting the current Miller circuit and three subcurrents are supplied to the predetermined three connecting points of the resistor chain. Hence, if a current (the emitter current of a transistor) flowing through an input bias circuit of each of the comparators in response to an input current of the comparator is I.sub.E, a total of 384 I.sub.E of current flows through the above-described transistors connected between the main transistor and minus terminal of the bias supply of the previously announced linearity compensation circuit. That is to say, to obtain three subcurrents 64i having the magnitude 64 times as great as the current i to be supplied to the input transistor of the comparator as the base current, the current 384 times as great as the emitter current I.sub.E of one transistor in the corresponding comparator must wastefully be caused to flow.
This causes remarkable increases in current flows through the linearity compensation circuit and in power loss in the A/D converter.